Cryogenic circuitry



April 20, 1965 J- J. LENTZ CRYOGENIC CIRCUITRY Filed June 13, 1962 DRIVER |07 l l l FIG.

'7 Sheets-Sheet 2 FIG.

FIG.

FIG.2

April 2o, 1965 J. J. LENTZ CRYOGENIC GIRCUITRY Filed June 13, 1962 '7 Sheets-Sheetl 3 i- STAGE Two STAGE THREE Ll'/ P15711 145,7 MNC 155 Thy r/15811 -L 1 1f/ A I 1211 L 1511s V 1 1 l]\\151s $2 April 20, 1965 J. J. LENTZ GRYOGENIC CIRCUITRY Filed June is, 1962 Q STAGE FOUR 7 Sheets-Sheet 4 FIG. 2c

7 Sheets-Sheet 6 J. J. LENTZ CRYOGENIC CIRCUITRY April 20, 1965 Filed June 13, 1962 April 20, 1965 J. J. LENTZ 3,179,815

CRYOGENIC C IRCUITRY FIG. 6

3,179,815 CRYGENC ClRCUTRY .lohn Il'. Leutz, Chappaqua, NY., assigner to International Business Machines Corporation, New York, NX., a corporation ot New York Filed .lune 13, 1962, Ser. No. 2%,537 14 Claims. (Cl. 3197-385) This invention relates to electrical circuitry and more particularly to high speed superconductive circuitry.

Cryogenic circuitry is generally organized in the form of loop circuits each of which has two current paths connected between a current source and a current collecting means. Each current path has a cryotron gate in series therewith which can be made resistive to cause the current to flow in the other current path. An output signal is obtained from each loop circuit by having the control element of an output cryotron connected in series with a current path of the loop circuit. Such loop circuits can be connected in chains between an input loop circuit and an output loop circuit. Each loop circuit in a chain (except the input loop circuit) is activated by the preceding loop circuit and each loop circuit (except, possibly, the output loop circuit) activates a succeeding loop circuit.

The magnitudeof the current applied to a loop circuit in combination with the resistance of the gating elements in the loop circuit determines a parameter of the loop circuit called the virtual power level ot the loop circuit. It the control elements and gating elements oi a loop circuit are of the crossed lm type the virtual power level of the loop circuit is equal to the product of one half the resistance of a gating element in the loop circuit times the square of the current supplied to the loop circuit. That is, with crossed film cryotrons the virtual power level of a loop circuit equals Rl2 where R is one half the resistance of one of the gating elements in the loop circuit and I is the current supplied to the loop cir* cuit. lf the control elements and the gating elements of a loop circuit are of the in-line type, the virtual power level of the loop circuit is equal to the product of one half of the resistance of one of the gating elements in the loop circuit times the magnitude ot the current supplied to the loop circuit. That is, with in-line cryotrons the virtual power level of a loop circuit equals RI where R is one half the resistance of one of the gating elements in the loop circuit and l is the current supplied to the loop circuit.

ln many instances it is desirable to minimize the time required for a signal to propagate through a chain of loops. One feature of the present invention is a means of minimizing the time required for a signal to propagate through a chain of loop circuits. A signal will propagate through a chain ot loop circuits in the shortest possible time if the virtual power level of each of the loop circuits in the chain including the rst and the last is identical. The `impedance level of the loop circuits in the chain may differ; however, so long as the virtual power level of the loop circuits is the same, a signal will propagate through the chain with a minimum amount of delay.

In certain instances, the virtual power level of two loop circuits, one ot which must drive the other, are determined by requirements of other circuitry to which the two loop circuits are connected. Hence, in certain instances a loop circuit which has a particular virtual power level must drive another loop circuit which has a diiierent virtual power level. Another feature of the present invention is the provision of a network which can propagate a pulse from a driving loop which has a certain virtual power level to a receiving loop which has a different virtual power level with a minimum amount of delay.

United States Patent O ice One object of the present invention is the provision of a cascaded series of loop circuits through which a signal can propagate with a minimum amount of delay.

Another object of the present invention is the provision of a cascaded series of loop circuits with various impedance levels, through which a signal can be propagated with a minimum amount of delay.

Another object of the present invention is to provide a network which minimizes the time required for a pulse to propagate from a driving loop which has a certain virtual power level to an output loop circuit which has a different virtual power level.

A further object of the present invention is to provide a circuit in accordance with the above object which has an optimum number of stages.

Another object of the present invention is to provide circuitry which minimizes the time delay experienced by a signal as it is propagated from one loop circuit to another loop circuit.

A further object of the present invention is to provide an amplifying chain between a driving loop which has one virtual power level and a receiving loop which has` a different virtual power level which minimizes the delay caused by the fact that the driving loop and the receiving loop have diiierent virtual power levels.

Another object of the present invention is to interpose the correct number of stages between a driving loop and a receiving loop so that signals are propagated from the driving loop to the receiving loop in the shortest possible time.

Yet another object or" the present invention is to provide circuitry in accordance with the foregoing objects which can be easily and reliably fabricated in thin iilm form.

Another object of the present invention is to provide circuitry in accordance with the foregoing objects which provides a simple, compact and eiiicient layout.

The foregoing and other objects, features and advantages ot the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.

FIGURE l is an overall schematic diagram of a first preferred embodiment. p

FIGURES 2a, 2b and 2c (which tit together as shown in FIGURE 2) are a layout diagram of the physical structure of the iirst embodiment.

FIGURE 3 is a layout diagram of the physical structure of a second preferred embodiment.

FIGURE 4 is a block diagram of a third preferred embodiment.

FIGURE 5 is a schematic circuit diagram of part of the circuitry shown in block form in FIGURE 4.

FIGURE 6 is a layout diagram of the physical structure of part of the circuitry shown in FIGURE 5.

FGURE 7 is a perspective view of part of the circuitry shown in FIGURE 6.

The first preferred embodiment of the present invention is shown in schematic form in FIGURE l. The actual physical structure of the circuitry is shown in FEGURES 2a, 2b and 2c (which yt together as shown in FIGURE 2). This lirst embodiment includes a driver l@ which has an output loop circuit 1l() and a receiver l2 which has an input loop circuit 15u. The virtual power level of loop lltl is ONE and the virtual power level of loop circuit 150 is EIGHTY-ONE. The characteristics of driver it) and of receiver 12; including the virtual power level of loop circuits lill and 150 is established by external considerations. Loop circuits 110 and ldd are interconnected by three loop circuits 12u, 13u and tdt'. Loop circuit lid controls loop circuit 1Z0, loop circuit tZti controls loop circuit 131), loop circuit 130 con- LD trols loop circuit 1t@ and loop circuit 14o controls loop circuit 151B.

The function of loop circuits 120, 13@ and is to provide Vmeans for transmitting a signal from driver 11B to receiver 12 in the shortest possible time. As previously stated a signal will propagate through a chain of loop circuits in the shortest possible time if the virtual power level of each of the loop circuits is equal. lf the current paths of loop 11@ were connected directly in series with the control elements of the cryotrons in loop v154i a signal will not propagate from driver 11i to receiver 12 in the shortest time because the virtual power level of the two loops is not equal. Hence, the interconnecting network which includes loops 12th, 13@ and 140 is needed.

Each loop circuit includes two current paths connected between a current source and a current collecting means. For example, loop circuit 12@ includes current paths 121 and 122 connected between current source 123 and current collecting means 124-. Current path 121 has a gating element 12S and the control element for gating element 135 connected in series therewith and current path 122 has a gating element 12o and the control'element for gating element 136 connected in series therewith. The control element for gating element 125 is connected in series withcurrent path 111 and the control element for gating element 126 is connected in series with current path 112.

When current is owing in current path 111, gating element 125 is resistive and hence the current from current source 123 flows in current path 122; and when current is i'iowing in current path 112, gating element 126 is resistive and hence, the Acurrent from current source 123 ows in current path 121. When the state of loop circuit 110 is changed by driver 1@ A(i.e., when current is switched from path 111 to 112 or vice versa) the state of loop circuit 126 is changed. Thus a signal is propagated frorn loop circuit 11@ to loop circuit 12d. Each of the other loop circuits is similar to loop circuit 12?, and signals are propagated between the other loop circuits in the same manner as explained above relative to loop circuits 11@ and 12).

ln order to facilitate reference between the specications and thedrawings, a uniform number scheme is used. A three digit numeral is used to designate each component in each loop circuit. The TENS digit of the numeral used to designate each element in any loop circuit is the same. The last numeral in the designation of any element is the same for each of the corresponding elements in each loop circuit. For example, the current paths in loop circuit 12@ are designated 121 and 122 and the corresponding current paths in loop circuit 13@ are designated 131 and 132. As shown in 111G- URES 2b and 2c, which show the physical structure of the circuitry, certain of the control lines traverse the associated gates more than once. F or example, as shown in FIGURE 2b, gating element 145 is traversed three times by the associated control element. For clarity of iilustration, in FIGURE l each control element is shown crossing the associated gate only once. In FIGURES 2a, 2b and 2c, the various segments of a control element which traverses a gate a plurality of times are all designated with the same number; however, the nurnbers are followed by different letters. For example, the control segments which traverse gating element 145 are designated 137a, 137!) and 137e. The three segments together are referred to as control element 137. Each junction where one loop circuit drives another loop circuit is hereinafter called a stage. Hence, the circuit shown in FGURES 1 and 2 has four stages.

One feature of the present invention is the interpositions of the correct number of loop circuits (i.e., the correct number of stages) between driver 1@ and receiver 12 which have different virtual power levels so that siglalswill propagate from driver 1@ to receiver 12 in the ,tenere E shortest possible time. The optimum number of stages which should be interposed between driver 10 and receiver 12 is equal to the closest integer to the natural logarithm of the virtual power level of loop circuit 1S@ divided by the virtual power level of loop circuit 111D. That is: if

where:

VPH0=the virtual power level of loop 11d. VP50=the virtual power level of loop 15?.

The optimum number of stages is given by the integer nearest n. Naturally as a matter of engineering practice the integer next lower than It might be chosen. lt can easily be seen that if the virtual power level of the driver and the receiver are the same, n is equal to the natural logarithm of one which is zero. Hence, where the virtual power level 'of the driver and of the receiver is the same no extra stages are needed. That is, where the virtuai power level of the driver and the receiver is the saine, the current paths of the driver can be connected directly in series with the control lines for the gating elements in the receiver loop if the two loop circuits are otherwise compatible.

In the particular embodiment shown herein the virtual power level of driver 11@ is ONE and the virtual power level of receiver 15u is ElGHTY-ONE, therefore n equals the closest integer to the natural logarithm of EIGHTY- ONE. The natural logarithm of EiGHTY-ONE is 4.39,V

hence, four stages are interposed between driver 1t) and receiver 12.

The plurality of stages between driver 1@ and receiver 12 must fulfill a further condition in order to propagate signals from driver 1t? to receiver 12 in the shortest possible tirne. Thiscondition is that the time delays introduced by each of the stages between driver 1t) and driver 12 must be substantially equal. The manner in which this is accomplished is explained later with reference to the physical structure shown in FIGURES 2a, 2b and 2c.

In the circuitry shown in FIGURES 2a, 2b and 2c each gating element is 3.2 times as wide as the control element in series therewith. That is, each gating element is 3.2 times as wide as the control element in the same current path. The ratio between the width of the gating element in a current path and the width of the control element in the same current path is a significant parameter hereinafter called K. The value of K is established by such considerations as the materials used to fabricate the circuitry, the operating temperatures, and the fabrication techniques. Though K has a value of 3.2 in all the circuitry shown herein, the present inventionis not limited to such circuitry. 1f the present invention is applied to circuits wherein the value of K is a value other than 3.2 the dimensions of each gate element or of each control element would change by an appropriate scale factor. Y

For convenience in the later description, a current of 2.0 amperes is hereinafter referred to as 1unit current, a width of 5.0 103 centimeters is hereinafter referred to as a unit width and a gating element (a) which is 3.2 units wide, (b) which has a control element of unit width and (c) which is crossed oniy once by the associated control wll hereinafter be referred to asa gating element which introduces two units of resistance into a current path. For convenience (except where otherwise indicated) the magnitude of each width, current and resistance will hereinafter be described with reference to the above unit current, unit width and unit resistance. The thickness of the gating elements, the insulating material, etc., is taken into account in the above units because in the particular embodiments shown herein the circuitry is uniform. That is, all the gating elements have the same thickness, all the insuiating material has the same thickness, etc. Naturally, the present invention is not restricted to the particular magnitudes shown in the preferred embodiment described herein and the invention is equally applicable to circuitry wherein other current magnitudes, circuit widths, and resistances are used.

The actual materials from which `the circuitry is fabricated and the method `of fabrication form no part of the present invention. For example, the gating elements may be made of tin and the circuitry other than the gating elements may be made of lead. As is conventional the cir` cuitryis deposited over a superconducting lshield in order to reduce the inductance of the circuitry.

As previously explained, each of the loop circuits 110, 120, 130, 1411 and 150 has a current source and a current collectingmeans (shown in FIGURE 1 by arrows). The current sources and current collecting means are shown in FIGURES 2a, `2b and 2c by stubs of circuitry designated 123, 124, etc. The manner of supplying current to the loop circuits is known and no explanation thereof is given herein. The magnitude of th'e current supplied to each `loop circuit is dependent upon the width of the control elements connected in series with the current paths of the circuit. A control element which is one unit wide requires one unit of current in order to generate enough magnetic field to make the associated gating element resistive. A control element three units wide requires three units of current to make the associated gating element resistive.

The width of each gating element, the Width of each control element, and the magnitude of `each current supply is tabulated below. The quantities are expressed in the previously explained system of units.

6 complished ii the. parameters of the various stages have values so that each of the following fractions is substantially equal to "e v(i.e., to the base of the natural logarithm).

Where R0=o`ne halt of the resistance introduced by each gating element in driver 1t?. For example, half the resistance introduced by gating element 115.

m1= the number of timeseaeh control line traverses the associated gating element in stage one. For example, the number of times control 117 traverses gating element 125. t

m2=the number of times each control line traverses the associated gating element in `stage two. For example, the number of times the control element 127 traverses the gating element 135.

m3=the number of times `each control line traverses the associated gating element in stage three. For example, the number of times control `element 137 traverses gating element 145.

m4=the number of times each `control line traverses the associated gating element in stage four. For example, the number of times control element 147 traverses gating element 155.

Wc1=the width of each control element in stage one.

For example, the width of control element 117.

W2=the Width of each control element in stage two.

For example, the width of control element 127.

Designation of Designation Width of Designation of Width of Designation Magnitude current path of gate gate element control element control of current oi current element element source source It was previously stated, that the characteristics of driver 1liand of receiver 12 are established by external considerations. For purposes of illustration, the driver 10 is shown in FIGURE 2a as including a current source 113 which supplies a current of unit magnitude and two gating elements 115 and 116 which are 3.2 units wide. Each of the gating elements 115 and 116 has an associated control line respectively elements 1117 and 10S. Each gating element is only traversed one time by the associated control line. Hence, in driver 10 the virtual power level, that is, theproduct of one half the resistance of one of the gating elements by the square of the current in the loop is ONE.

For purposes of illustration, receiver 12 is shown as including current source 153 which supplies three units of current and two gating elements and 166. The control elements 157 and 158 for gating elements 165 and 166 are connected in series with current paths 151 and 152 and they only traverse the respective gating elements once. The width of the control elements 157 and 158 is three units. It should be emphasized that the virtual power` level of driver 111 and of receiver 12 is established by external considerations. The virtual power levels of driver 141 may, for example, be established by the requirements of control lines 107 and 1118, and the virtual power level of receiver 12 may, for example, be estabiished by the requirements of gating elements 165 and 166.

One of the requirements for minimum total delay is that the delays introduced by each stage must be substantially equal. To an engineering approximation this is ac- Wcgzthe width of `each control element in stage three.

, For example, the width of control element 137:1.

Wc=the width of each control element in stage four.

For example, the widthof control element 14711.

For the general case, where more than four stages are required, the expression can be written as follows:

Where:

j=the parameters of the last stage. f j1=the parameters of the next to the last stage. rztheparameters of the receiver.

mi Wei i m2 W03 Ins Wai mi Wes 1 3 l. 3 3 3 `9 3 1 l. l 1 l 3 3 3 Ru Wel mi Wei 1312 W02 1113` Wea Each box in the above chart contains a number plus a designation of what the number` represents. From the above chart it is easily seen that in the preferred embodiment shown herein each of the terms `in the expresison` has a value of three. Hence, a signal is propagated from driver 1t? to receiver 12 in substantially the` shortest possible time. Note that as a matter of engineering consnr/asisA venience integral values have been assigned to all parameters.

A second preferred embodiment of the invention is shown in FIGURE 3. This alternate embodiment of the invention includes a driver 20 which has a virtual power level of ONE and a receiver 2li which has a virtual power level of TEN. A network 2l is interposed between driver 2l) and receiver 22 so that signals will propagate from driver 2i) to receiver 22 in the shortest possible time.

As in the previous example, the number of stages in network 21 is equal to the nearest integer of the natural logarithm of the virtual power level of receiver 22 divided by the virtual power level of driver 20. That is,

where n=the number or" stages (nearest integer). VP22=the virtual power level of receiver 22. VP20=the virtual power level of driver Ztl.

ln tergms of the driver Ztl and receiver 22,

current paths 231 and 232 of receiver 22 respectively have gating elements 235 and 236 connected in series therewith. n

ln each of the circuits shown in EGURE l2, where a control element traverses a gating element, a plurality of times, the gating element is constructed as one segment and there is no circuitry connected between the places where the control element traversed the gating element at diierent points. ln this embodiment of the invention the gating element in current paths 221 and 222 are divided and between the points where control 217 traverses gatev 22S, some of the segments of control 227 are connected. rThat is, segments 227g, 22712 and 227C are connected in series between gate segments 225a and 22517. Likewise the gate segments 225b and 225e are connected in series between control segments 227C and 22761. Electrically, the construction shown above is identical to the type of construction shown in FIGURE 2. However, the construction shown above provides a more etcient layout. hat is, the circuitry occupies less surface area.

rl`he width of each gating element, the Width of each control element and the magnitude of each current supn=1n 1 0=2 3 ply is tabulated below. The quantities are expressed in the previously explained system of units.

Designation Designation of Width of Designation Width of Designation Magnitude of current gate element gate of control control of current of current path element element element source source g Not shown. 1. 223 1 1.0 223 1 233 1 233 l Y The closest integer is two so two stages are interposedV between driver Ztl and receiver 22.

As in the rst embodiment, the number or" loop circuits interposed between the driver and receiver 22 is one less than the number of stages. Hence, in the second embodiment only one loop circuit is interposed between driver l@ and receiver 22. The loop circuit at the output of driver 2@ is designated 213.0, `the loop circuit which is interposed between driver 2d and receiver 22 is designated 22d and the loop circuit of receiver 22 is designated 23d. The two current paths of loop circuit 2li) are designated 2li and 2112, the two current paths of loop circuit 220 are designated 221 and 222 and the two current paths of loop circuit 230 are designated 231 and 232. Loop circuit 21d has a current collecting means 2ll4, loop circuit 22th has a current source 223 and a current collecting means 22d and loop circuit 23d has a current source 233.

Current paths 221i. and 222 of loop circuit 220 each have a gating element and a control element connected in series therewith as did each of the loop circuits shown in FIGURE l. However, one of the novel features of Vthis second embodiment of the invention is that the gating element connected in series with each of the current paths 221 and 222 is divided into a plurality of segments. The gating element connected in series with current path 221 is in general designated 225 and the three segments thereof are designated 225g, 22517 and 225C, and the gating element connected in series with current path 222 is in general designated gating element 226 and the three segments thereof are designated 226e, 226b and 226e. The control element connected in series with current path 221 is in general designated 227 and the segments thereof are designated 227e, to-227j. The control element connected in series with current path 222 is in general designated control element 222 and the segments thereof are designated 228:1 to 223]'. Current paths 2li and 2112 of driver Zit respectively have control elements 217 and 21% connected in series therewith and m1 Ww m2 Wes 3 1 10 l 1 1 3 l Ru We; mi f W c 1 It should be noted that the rirst term mlWcz RcWcr is equal to three and that the second term 12V/'c3 mlWcl is equal to three and one third. That is, the terms are not exactly equal. Since each of the terms is not exactly equal to e, a time delay introduced by each loop circuit is not exactly equal and a signal is not propagated from driver 2@ to receive 22 in the absolutely shortest possible time. However, since the value of each of the terms in the expression is greater than two and less than three and one half (i.e., each term is substantially equal to e) signals are still propagated from the input 2% to the receiver 22 in substantially the shortest possible time. lf the value of each of the terms is not substantially equal to e, the propagation time is increased appreciably. That is, when the value of each term is between two and `virtual power level of each loop circuit is given bythe product of one half the resistance of one of the gating elements in the loop circuit times the square of the current applied to the loop circuit, that is, RI2 where R is one halfthe `resistance of one of thegating elements in the loop. If the cross-hlm cryotrons show-n herein are replaced by in-line cryotrons the virtual power `level of each loop circuit is equal to the product `of one half the resistance of one of the gating elements in each loop circuit times the current applied to the loop circuit, that is, RI. Hence, `if in-line instead `of cross-nlm cryotrons are used, all the previous discussion applies, except that the virtual power level ofthe loops is calculated as RI instead of RIZ.

A third preferred `embodiment of the invention is shown in FIGURES 4, 5, '6 and 7. As shown in block form in FIGURE 4 `this embodiment includes an input 10'., four `drivers A to D,.four output groups J to M and `sixteen outputs `O1 to O16. FIGURE 5 is an electricalschematic diagram of the circuitry. It should be noted that for ease of illustration and due to the repetitions .nature the circuitry the details of output groups L `andtclriver D `are'not shown in FIGURE 5. FIGURE 6 ishows a physical layoutof a representative portion of the circuitryand FIGURE 7 is a perspective view of the physical layout of a representative portion of the circuitry.

This embodiment includes nine cascaded loop circuits fourfof which have one impedance level and'four of which `have another impedance level; however, each of the -loopcirctiits has the same virtual power level. Since each `of the cascaded loop circuits has the same virtual power rlevel, a signal is` propagated from the tiret loop circuit to the last loop circuit with a minimum amount of delay.

In order to facilitate reference between the specification and the drawings each component in FIGURE is designated by a numeral followed by a letter. Similar components which are located in diiIerent drivers or in diiferent output groups are designated by the same numeral and the letter which follows the numeral designates the par- `ticulardriver or the particular output group with which the particular component is associated. For example, `driver A has a line designateddZA andthe corresponding line in driver B is designated 42B.

The portion of the circuitry shown in FIGURE 5 in `the bold lines designates the portion of the circuitry which is used to explain the physical structure of the device. The physical structure and layout of that portion of the circuitry .in drivers A and B and output groups I and K which is shown in bold lines in FIGURE 5 is shown in `FIGURE 6. As shown in FIGURE 4 input 10' activates driver A which in turn activates output set I and driver B. Driver `B activates output set K and driver C, etc. Input 10', each of the drivers A to D and each of the output sets] to M are formedby loop circuits. Each of the loop circuits has two current paths connected between a current source (designated in FIGURE 5 by a terminal) and a current collecting means (designated in FIGURE 5 by a ground ,.symbol). -Each current source constantly supplies a current (the magnitude of which will be explained later) and thecircuitry operates so that there is current in one and only one of the current paths in any loop circuit at any particular time.

Each current path in each loop circuit has a reference numeral, anda loop circuit is designated `by the numerals which designate the two paths of the loop circuit. For example, the loop circuit in driver A which includes cur rent paths 22A and 42A is designated as loop circuit 22A-42A.

Driver A includes current paths 22A and 42A which are connected to a current source A to form loop circuit 22A-42A. Driver A also includes a part of current paths 21 and 41 which form loop circuit 2l41, anda part of current paths 23A and 43A which are connected to a current source 61A to form loop circuit 23A-43A. Current path 22A has a cryotron gating element ZZAG connected in series therewith. The control line for cryotron gating `element ZZAG is connected in series with `current path 21. Current path 42A has a cryotron gate Velement ZAG connected in series therewith. The control line for a cryotron gating element 42AG is connected in series with rcurrent path 41. Current paths 23A `and A43A `have cryotrongatingelements ZSAG and ISG respectively connected in series therewith. The control lines for cryotron gating elements 23AG `and 43AG are respectively connected in series with current paths 22A and 42A.

Input l0' may be similar in structure to driver It) shown in FIGURE 2a; however, the gating elements therein must be similar to gating element `MAG. Input 14) constantly supplies current to either current path 4l or to current path 21 and it supplies a signal to the circuit by changing current from current upath il to `current path 2l or vice versa. When the state of loop circuit 21-41 is changed, the state of loop circuit :22A-42A is changed through `cryotron gate ZZAG and 42AG and similarly `when `the `state of loop circuit 22A-42A is changed `the state `of loop circuit 23A-43A is changed.

'Output `group I includes eight current paths 24J to `27J and 44] to 47]. `Current paths 24] to 27] and 44] to 47] together with four `current sources `62]' to 653 form 'four output loops 24J-44] to 27I-47J, alternately designed O-1 to O-4. Output group I also includes *a portion of current paths V23A and V43A vand eight` identical cryotron gating elements 24JG to Z7IG and MIG to 47JG which are respectively connectedin series with current paths 24] to 2`7J `and del to 47].

Loop circuit 23A-43A controls the state of each of the output loop circuits 24S-44S to 273-478 in the same manner that loop circuit 21-41 controls the state of loop circuit `22A-442A. The `current paths in each of the output `loops 24J-44] to 27I-47I (alternately designated outputs 0 1 to O-4)'control a plurality `of output cryotrons designated OC. The output cryotrons OC are connected in utilization circuitry not shown'herein.

Drivers B, C and D are each identical to previously described driver A, hence, no detailed description thereof will be given. It is noted that driver B is activated by loop circuit 23A-43A similar to the manner in which driver A was activated by loop circuit 2141. 'Each of the other output groups K, L and M is identical to output group I. Herein for ease of illustration each loop 'circuit is shown connected `between a Vseparate current Asource and ground. Many of the separate current sources could be eliminated by connecting loopcircuits in Vseries as is known in the art.

The physical structure of selected `representative .portions ot the circuitry is yshown in FIGURES -6 and 7. The particularportions of drivers A and B and output sets I and K which are shown in FIGURES 6 and 7 are `indicated in FIGURE 5 with bold lines. FIGUR-E '6 is a top view and FIGURE 7 is a perspective view of a portion ot the circuit shown in FIGURE 6. For clarity of illustration no insulating material is shown in FIGURE 6i however, as shown in FIGURE 7 the various conductors are separated by layers of insulating material 71. The entire structure is mounted on a substrate 711. Directly above the substrate is a superconducting shield 712 which is used to reduce inductance and to serve as the return path for current as is conventional in the art. The use of a shield for these purposes is Awell known.

The portion ot driverA shown in FIGURE 6 includes a portion of current paths 4l, 452A and 43A. Current path 42A has a cryogenic gating element dZAG connected` in series therewith and current path 43A includes cryogenic ten units of current.

a il. l. gating element 43AG connected in series therewith. Curl rent path 4I which passes over and serves as the control element yfor gate element 42AG is connected to input Iii (not shown in FIGURE 6) at point 4ta and is connected to shield I2 at point 4llb. Current path 42A which passes over and serves as a control element' for gate element 43 is connected to current source 66A (not shown in FIGURE 4) at the end designated 42Aa and it is connected to the shield I2 at the point designated 42Ab. The shield 712 is therefore used as the return path for the current in the various conductors.

Similar to the manner in which the bold lines in FIG- URE 5 indicate those portions of driver A which are shown in FIGURE 6, the bold lines in FIGURE 5 also indicate the portions of output group l which are shown in FIGURE 6. The portions of output group I which are shown in FIGURE 6 include portions of current paths 43A, 441,451, del and 47I and cryotron gating elements 44IG, 455C?, 46IG and 4'7JG. FIGURE 6 also shows a portionof current path 42B and 43B and gating elements @ZEG and 43BG which are part of a driver B and a portion of current paths 43B, 44K, 45K, 46K and 47K and gating elementsdtKG, 45KG, 46KG and 4'7KG from output group K.

Similar to the previously described circuitry, in each current path the gating element in series with the current path is 3.2 times as wide as the control elements in series with the same current path. That is, the parameter k has a value of 3.2. As previously stated the present invention is not limited to circuitry which'has a value of kV equal to 3.2 and if the circuitry had a different value of k the appropriate dimensions would merely be changed by a scale factor.

The portions of driver A and output group not shown in FIGURE'6 are identical in construction to the portions shown, hence, no explanation thereof is given. Likewise each of the other drivers is identical in construction to driver A and each of the other output groups is identical in construction to output group I hence, no explanation thereof is given.

The width of each control element and of each gating element is driver A and in output group J is tabulated below. The dimensions are given in the previously explained system of units.

Width of control elements connected in series therewith Designation o gating element connected in series therewith Current path Width ofgating element 1.0 Not shown o do NICNLQLQO Current sources connected to current paths 41, 43A and 44] to 4'7J each supply one unit of current and the current source connected to current path 42A supplies It is noted that the current source for current path 41 is inside input itl and it is not explicitly shown.

The physical width of current path 43A diters along its length. The three diiferent widths are designated x, y and z. The length of each of the four control elements which control gating elements MIG to #WIG is designated r and the length of each segment which connects `the control elements is designated s.

The reason that the dimensions of the circuitry are as shown'is that the circuitry acts as a plurality of transmission linesand the impedance of the transmission lines must he properly related to the impedance of the drivers. Such circuitry is shown in U.S. Patent 2,962,681 entitled Superconduotor Circuits by lohn I. Lentz which is assigned tothe assignee of the present invention.

The actual dimensions depend upon the particular ma- Yta terial used in structure. If each of the -gating elements is rnade of an alloy material, such as that described in copending application by R.V P. Reeber, Serial No. 814,495 entitled Superconductive Components (IBM Docket l0, 139) which is assigned to the assignee of the present invention, and it' the thickness of insulation 71`is 10-5 cm., in order to properly relate the impedance 'of the current paths such as current path 43A to the resistance of the gating elements 43AG, the transmission line must have an impedance equal to approximately 0.09` ohm and the various lengths have the following values:

x=5 10-3 cm. r=0.016 cm.

A pulse is propagated through the nine cascaded series Y of loop Vcircuits from loop circuit 2li-4I to loop circuit 23M-d3M with a minimumY amount of delay because the virtual power level of each of the loop circuits is the saine. The virtual power level of each of the cascaded loop circuits is equal to TEN.

The nine cascaded loop circuits which have the same virtual power level are loop circuits (l) 2I-41; (2) 22A-42A; (3) 23A-43A; (4) 22B-42B; (5) 23E-43B; (6) 22C-42C; (7) 2SC-43C; (8) 22B-42D; (9) M13-43D. Hence, signals are propagated through the above nine loops with a minimum amount of delay and the state or" cryotrons 24] G to ZMG and 44] G to 47MG is changed with a minimum amount of delay. Loop circuits O-l to @-16 have different virtual powerl levels and hence they do not change state with a minimum amount of delay; however, this is of little consequence because the added amount of delay from each of these loop circuits is not cumulative.

The virtual power level of the loop circuits in the drivers, i.e., loop `circuits 22A-42A; 22B-42B; etc., is calculated as follows: The resistance of each gating element such as gating element 42AG is one-fifth unit (since the gating element is 32.0 units wide and the control element is one unit wide) and the current Vsupplied to each of these loop circuits has a magnitude of ten'units. Since the circuits are made of crossed lm cryotrons, the virtual power level of a loop circuit is equal to the product of one-half the resistance of one of the gating elements times the square of the current supplied to the loop circuit. For loop circuits 22A-42A, 22B-42B, etc., that equals TEN. The virtual power level of the loop circuits in the output groups, i.e., loop circuits 23A-43A, 23B-43B, etc., is calculated as follows. The resistance of each gating element suchas gating element 43AG is twenty units (since the gating element is 3.2 units wide and the control element is ten units wide) and the magnitude of the current supplied to each loop circuit is ONE. Since the virtual power level equals the product of one-halt' the resistance times the square of the current, it equals TEN.

It should be particularly noted that the virtual power level of the various loop circuits is equal even though the impedance level of the various loop circuits is not equal. That is, the chain of loop circuits shown is a minimum delay chain of loop circuits even though the loop circuits have different impedance levels. y

Since the virtual power level of eachrof the loop circuits is equal, the time delay introduced by each of the loop circuits in the chain is equal. This can be easilyV seen from the following table from which it can be seen that the value of each of the ratios in the previously given expression is equal to TEN. As previously explained this shows that the time delay introduced by each of the loop circuits is equal.

' mi Wcz 1m Wea l l0 l l 10 1 1 1 Ru Wei mi Wei where R equals one-half the resistance of gating element 43AG.

m1 equals the number of times current path 43A crosses `gating element 42BG.

m2 equals the number of times current path 42B crosses gating element 43BG.

WC1 equals the width of the control element associated with gating element 42BG.

W62 equals the width of the control element associated with gating element 43BG.

WC3 equals the width of each control element connected in series with current 43B.

The same ratio can be calculated for the other loop circuits with similar results.

Certain of the loop circuits could be eliminated from the current. For example, current path 41 could be directly used as a control element for gating element 43AG and current path 42A could be eliminated, in this instance, current path 41 would have `to traverse gating element 43AG ten times in Aorder to get the correct impedance level. Due to the shape `of the masks needed, such a structure would be more dirlicult to fabricate than the structure shown herein.

The reason that a cascaded series of loop circuits is used instead of connecting current paths 21 and 41 directly in series with the control elements for cryotrons 24J G to 271cv, 44IG to 471 G, 24KG to 27KG, MKG to 47KG, etc., is due to the terminal limitations on the input That is, with a cascaded series of loop circuits (i.e., with a subdivided line) the circuitry can operate at a higher repetition rate without exceeding the thermal limitations of the circuitry since each loop circuit only activates a relatively limited number `of other loop circuits.

No specific denition for thetime delay of a loop circuit has been given since the manner of dening time delay is not particularly relevant to the invention. The time delay introduced by a loop circuit may, for example, be defined as thetime between when the gating element in the current path of a loop (ie, the current path which is carrying current at a particular time) begins to become resistive and when suicient current is shifted into the other current path of the loop circuit so that the `control `element in series therewith begins to make the associated gating element resistive.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

What is claimed is:4

l. A cryogenic network for interconnecting a` driver circuit` to :a receiver circuit, said driver and said receiver each having a different virtual power level, said'network comprising:

a plurality of cryogenic loop circuits cascaded in stages, each loop circuit having a current source, a current collecting means and two parallel current paths conp necting said current source to said current collecting means, each current path having a gating element and a control element'connected in series therewith,

the `number of stages interposed between said driver and said receiver being equal to the closest integer to the natural logarithm of the virtual power level of said receiver divided by the virtual power level of said driver.

2. A cryogenic network for interconnecting a driver loop circuit to a receiver loop circuit, said driver loop circuit and said receiver loop circuit having different virtual power levels,`said interconnecting network having a plurality of cryogenic loop circuits cascaded in stages, fthe time delay ,of` each of said cryogenic loop circuits being substantially equal,

the number of stages interposed between said driver and said receiver being equal to the closest integer to` the natural logarithm of the virtual power level of the receiver divided by the virtual power level of the 5 driver.

3. A cryogenic network for interconnecting a driver circuit to a receiver circuit, said driver and said receiver having dierent virtual power levels, said network comprising:

a plurality of cryogenic loop circuits cascaded in stages, each loop. circuit having Va current source, a current collecting means and two parallel current paths connecting said current source to said current collecting means, each current path having a gating element and a control element connected in series therewith,

the time delay ofeach of said loop circuits being substantially equal,

the number of stages interposed between said driver and said receiver being equal to the closest integer to the natural logarithm of the virtual power level of said receiver dividedv by the virtual power level of said driver.

4. A network for connecting a driver to a receiver said driver and said receiver having different virtual power levels, said network comprising,

a plurality of stages equal to the closest integer to the natural logarithm of the virtual power level of the receiver divided by the virtual power level of the driver,

each of said stages comprising two cryotron gating elements controlled by two cryotron control elements,

means connecting the cryotron control element in each lstage in one loop circuit and the cryotron gating elements in each stage in a different loop circuit,

tural power levels, said driver loop circuit and said receiver loop circuits having a current source, a current collecting means, two current paths interconnecting said `current source and said current collecting means, each of said current paths including a cryogenic gating element `and a control element, said gating element introducing two times R0 units of resistance into the associated control path when said gating element is resistive,

said network comprising a plurality of cryogenic loop circuits l to j cascaded in stages, each loop circuit having a current source, current collecting means and two parallel current paths connecting said current source to said current collecting means, each current path having a gating element and a Ycontrol element connected in series therewith, said control element traversing the associated gating element m1 to mj times respectively, said control. element being W1 to WJ- units wide respectively, the parameters of said loop circuits being such that each of the terms inthe following expression is substantially "equal:

mi Wer a control element, said gating element introducing two each of said loop circuits comprising a current source,

times Rv units of resistance into the associated control path when said gating element is resistive,

said network comprising a plurality of loop circuits l to j cascaded in stages, each loop circuit having a current source, current collecting means and two parallel current paths connecting said current source to said current collecting means, each current path having a cryogenic gating element and a control element connected in series therewith, said control element traversing the associated gating element m1 to mj times, respectively, said control element being W1 to Wj units wide respectively, the parameters of said loop circuits being such that each of the terms in the following expression RoWt-i miWez is substantially equal,

the number of stages interposed between said driver loop circuit and said receiver loop circuit being equal to the closest integer to the natural logarithm of the virtual power level of the receiver divided by the virtual power level of the driver.

7. A cryogenic network for interconnecting a driver loop circuit having a virtual power level of ONE to a receiver loop circuit having a virtual power level of EIGHTY-ONE, said network comprising;

a plurality of cryogenic loop circuits cascaded in four stages between said driver loop circuit and said reiver loop circuit,

the time delay introduced by each of said loop circuits being substantially equal,

whereby a signal is transmitted from said driver loop circuit to said receiver loop circuit in substantially the shortest possible time.

y8. A cryogenic network for interconnecting a driver loop circuit having a virtual power level of ONE to a receiver loop circuit having a virtual power level of TEN, said network comprising;

a plurality of cryogenic loop circuits cascaded in two stages between said driver loop circuit and said receiver loop circuit,

`the time delay introduced by each of said cryogenic loop circuits being substantially equal,

whereby a signal is Vtransmitted from said driver loop circuit to said receiver loop circuit in substantially the shortest possible time. n

9. First, second and third cascaded cryogenic loop circuits,

each of said loop circuits comprising a current source,

. current collecting means, and two parallel paths connecting said current source to said current collecting means, each of ysaid current paths including `a cryogenic gating element and a control element,

the gating element in said second loop circuit being divided into a plurality of sections and the control element in said rst loop circuit being divided into n a like plurality ofsections, the plurality of sections of 4the control element in said rst loop circuit being connected in series and the plurality of sections of the gating element in said second loop circuit being connected in series,

the gating element in said third loop circuit being divided into a plurality of sections and the control element in said second loop circuit being divided into a like plurality of sections, said plurality of sections of the gating element in said third loop circuit being connected in series and the plurality of sections of the control element in said second loop circuit being connectedin series,

certain of the sections of the gating elements in the Vcurrent, paths of said second loop circuit being separated by sections of control element whereby in the current paths of said second loop circuit certain sections ot gating element are separated from the rel@ maining sections of gating element by sections ot"A control element. 10. A cryogenic network for interconnecting a driver loop circuit having a virtual power level of ONE. to a receiver loop circuit having a virtual power level of ElGHTY-ONE, said network including irst, second and third cryogenic loop circuits cascaded in four stages between said driver loop and said receiver loop,

each loop circuit including a current source, current collecting means, two parallel paths connecting said` current source to said current collecting means, each of said current paths including a gating element and a control element,

the control elements in said driver loop circuit being one unit wide `and crossing the gating element of said second loop circuit one time,

the control elements in said iirst loop circuit being three units wide and crossing the gating elements in said second loop circuit one time,

the control elements in said second loop circuit being three units wide and crossing the gating elements in said third loop circuit three times,

the gating elements in said third loop circuit being three units wide and crossing the gating elements in said receiverloop circuit nine times,

whereby a signal is propagated from the driver loop to the receiver loop in substantially the shortest possible time.

11. A composite transmission line for transmitting signals from an input to a plurality of outputs,

said transmission line comprising a plurality of cascadedV cryogenic loop circuits, each loop circuit in said transmission line having two current paths connected between a current source and a current collecting means, each of said current paths including a control element and a gating element connected in series therewith,

a plurality of said loop circuits each actuating a plurality of said outputs,

the virtual power level of each of said loop circuits being equal,

whereby signals are transmitted from said input to each of said outputs with a minimum amount of delay.

l2'. A cryogenic circuit comprising,

a plurality of cryogenic loop circuits cascaded between an input loop circuit and an output loop circuit, each of said cryogenic loop circuits having the same virtual power level, whereby a signal is propagated from said input loop circuit through each of said loop circuits to said output loop circuit in substantially a minimum amount of time.

13. A cryogenic circuit comprising a series of cascaded cryogenic loop circuits,

each of said cryogenic loop circuits comprising a current source, current collecting means, two current paths connecting said current source to said current Y collecting means, each of said current paths including gating element and control elements,

the control elements connected in series with the current paths of each loop circuit being associated with the gating elements connected in series with the current pathsy of the next loop circuit in the series,

the virtual power level of each of said loop circuits being the same,

whereby a signal is propagated from the iirst cryogenic loop circuit in the series to the last cryogenic loop circuit -in the series with the minimum amount of delay.

14. A cryogenic circuit comprising a plurality of cryogenic loop circuits cascaded7 in series, said loop circuits being divided into a plurality of dierent classes, each loop circuit in each class having the same impedance level, the loop ycircuits in i7 18 each class having a diierent impedance level from 0 Reei'ences Cite by the Examiner the loop circuis in the other classes, UNITED STATES PATENTS each of said cryogenic loop circuits having the same 3 019 354 1/62 Anderson et al 30,7 88 5 fm1 POW level 3,056,041 9/62 Davies 307-885 whereby a signal is propagated through said series of 5 loop circuits with a minimum amount of delay. ARTHUR GAUSS, Primary Examiner. 

1. A CRYOGENIC NETWORK FOR INTERCONNECTING A DRIVER CIRCUIT TO A RECEIVER CIRCUIT, SAID DRIVER AND SAID RECEIVER EACH HAVING A DIFFERENT VIRTUAL POWER LEVEL, SAID NETWORK COMPRISING: A PLURALITY OF CRYOGENIC LOOP CIRCUITS CASCADED IN STAGES, EACH LOOP CIRCUIT HAVING A CURRENT SOURCE, A CURRENT COLLECTING MEANS AND TWO PARALLEL CURRENT PATHS CONNECTING SAID CURRENT SOURCE TO SAID CURRENT COLLECTING MEANS, EACH CURRENT PATH HAVING A GATING ELEMENT AND A CONTROL ELEMENT CONNECTED IN SERIES THEREWITH, THE NUMBER OF STAGES INTERPOSED BETWEEN SAID DRIVER AND SAID RECEIVER BEING EQUAL TO THE CLOSEST INTEGER TO THE NATURAL LOGARITHM OF THE VIRTUAL POWER LEVEL OF SAID RECEIVER DIVIDED BY THE VIRTUAL POWER LEVEL OF SAID DRIVER. 